1. Field of the Invention
The present invention relates to an active matrix substrate used for a display device, e.g., a liquid crystal display device, and a display device incorporating the active matrix substrate.
2. Description of the Related Art
A liquid crystal display device is known which includes an active matrix substrate (having an equivalent circuit shown in FIG. 10) as one of a pair of substrates interposing a liquid crystal layer. The active matrix substrate includes thin film transistors 2 (hereinafter referred to as "TFTs") for controlling the turning on/off of pixel electrodes, the TFTs 2 being arranged in a matrix. A gate line 3 is coupled to a gate electrode of each TFT 2, so that the TFT 2 is driven in accordance with a signal provided via the gate line 3. A source line 5 is coupled to a source electrode of each TFT 2, so that a video signal or the like provided via the source line 5 is input to the corresponding pixel electrode (via the source electrode and drain electrode of the TFT 2) while the TFT 2 is maintained ON by a signal applied to the gate line 3. One of the terminals of a pixel capacitance 1 (a plurality of which constitute a matrix) is coupled to the drain electrode of each TFT 2. The other terminal of each pixel capacitance 1 is coupled to a pixel capacitance line 4. When a liquid crystal cell is formed by interposing a liquid crystal layer between the active matrix substrate and a counter substrate, the pixel capacitance line 4 is coupled to an opposing electrode formed on the counter substrate.
FIG. 14 is a plan view showing an active matrix substrate having the above-mentioned equivalent circuit. FIG. 15 is a cross-sectional view taken at line B-B' in FIG. 14 (corresponding to one pixel portion). FIG. 16 is a plan view showing a TFT portion on the active matrix substrate. The active matrix substrate is composed essentially of a transparent insulating substrate 10 having source lines 5 and gate lines 3 formed thereon, with a TFT 2 being formed in the vicinity of each intersection of the source lines 5 and gate lines 3.
As shown in FIG. 15, the TFT 2 is formed on a gate electrode 11, which extends from the gate line 3. A gate insulating film 12 is coated over the gate electrode 11. A semiconductor layer 13 is formed on the gate insulating film 12 above where the gate electrode 11 is formed. A channel protection film 14 is further formed on the semiconductor layer 13 above where the gate electrode 11 is formed. A source electrode 15a and a drain electrode 15b (both composed of an n.sup.+ Si layer) are formed on the semiconductor layer 13 and the gate insulating film 12, the source electrode 15a and the drain electrode 15b being disrupted from each other at the channel protection film 14. A transparent conductive film 16' is formed so as to partially overlap the source electrode 15a and the drain electrode 15b. A metal layer 16 is formed on the transparent conductive film 16'. Thus, the transparent conductive film 16' and the metal layer 16 on the source electrode 15a side constitute a double-layered source line.
An interlayer insulating film 17 and a pixel electrode 6 (within a bold line) formed of a transparent conductive layer are formed in this order on the above-described substrate. Both the interlayer insulating film 17 and the pixel electrode 6 extend over an area wider than the TFT 2 itself. The pixel electrode 6 is coupled to the drain electrode 15b of the TFT 2 via a contact hole 7 through the interlayer insulating film 17.
On the active matrix substrate having the above configuration, the interlayer insulating film 17 exists between the pixel electrode 6 and the gate line/source line. As a result, it is possible to lay out the pixel electrode 6 so as to overlap the gate line and/or the source line, thereby improving the aperture ratio of the display device and shielding any electric field arising due to the signal lines. Such a structure is disclosed, for example, in Japanese Laid-Open Patent Publication No. 58-172685.
However, the above-mentioned conventional active matrix substrate including inverse-staggered TFTs has a problem in that the characteristics thereof drastically change with the lapse of time during which a voltage is applied to the TFTs (hereinafter referred to as "voltage application time").
FIG. 11 is a graph illustrating the OFF-characteristics of the TFTs assuming a case where a black image is displayed all across the display. In FIG. 11, the abscissa axis shows the voltage application time for the TFTS, and the ordinate axis shows the low level (Vgl) of the potential of the gate line. The graph was obtained by varying the low level (Vgl) of the gate line while applying a signal of .+-.3.5 V to the source line and plotting levels at which the displayed image reversed to a white image.
As seen from FIG. 11, a larger value of Vgl provides a larger margin in the OFF-characteristics of the TFTs. For example, when a conventional active matrix substrate (shown by curve A) is driven under the condition Vgl=-8V, the active matrix substrate starts malfunctioning (i.e., the black image reverses to a white image) after 200 hours of voltage application, indicating the substrate's life being only so many hours. Such an active matrix substrate clearly does not withstand the actual use. This deterioration in the OFF-characteristics is especially marked in the case where a thin organic film is used as the interlayer insulating film.
Moreover, the active matrix substrate is subject to a "haziness" phenomenon (i.e., in a NW (normally-white display mode) the displayed image appearing more whitened than is normal) in response to any shift in the OFF-characteristic of the TFTS. This phenomenon considerably deteriorates the display quality of the device.